1. Field of the Invention
This invention generally relates packaging techniques and structures for microelectronic devices, and more particularly, to a methods and structures relating to pin grid array chip carriers.
2. Discussion of Related Art
In the fabrication of substrates and carriers for microelectronic components such as integrated circuit chips, the use of pin grid arrays (PGAs) is well known. Discussions of the background art have been published. See, for example, Rao R. Tummala and Eugene J. Rymaszewski, Microelectronics Packaging Handbook, Van Nostrand Reinhold, New York (1989), at 785, et seq. During the fabrication of a chip carrier for a PGA package, the attachment of individual pins by brazing to input/output (I/O) pads on the chip carrier substrate is also well known. The following references illustrate the state of the pertinent art.
U.S. Pat. No. 5,033,666 to Keusseyan, et al., discloses a process for brazing metallized components to ceramic substrates.
U.S. Pat. No. 5,567,984 to Zalesinski, et al., discloses a process for fabricating electronic circuit packages such as PGAs.
U.S. Pat. No. 5,491,362 to Hamzehdoost, et al., discloses package structures such as PGAs.
In the case of ceramic substrates, a number of pin brazing techniques use silver-copper (or "copper-silver") braze to attach pins to the I/O pads on the substrates. It has been found in some instances that silver migration between the I/O pads causes shorts and other disadvantages and deleterious effects. The silver migration is caused by wetting of the ceramic surface with silver in the region around the I/O pads. Subsequent nickel and gold plating over the brazed region is not sufficient to seal off the silver-copper braze at the edges of the I/O pads.
It would thus be desirable to provide a method for removing excess silver-copper braze material from chip carrier substrates to solve the aforesaid and other deficiencies and disadvantages.